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Verilog用Modelsim仿真时错误:Instantiating 'u_state_machine_pkt_top' has exceeded the recursion depth limit

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错误信息:Instantiating 'u_state_machine_pkt_top' has exceeded the recursion depth limit of 200.错误信息:Instantiating 'u_state_machine_pkt_t




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