1、实验内容：Xilinx Design Constraints设计约束
You will start the project with I/O Planning type, enter pin locations, and export it to the rtl. You will then create the timing constraints and perform the timing analysis创建一个I/O Planing类型的工程，输入相应管脚位置，然后将它输入rtl，再创建一个时序约束，并进行时序分析You will
