如何使用Quartus II将我的clockDivider连接到这个verilog程序中

Code:

TestBench.v:

// ============================================================
//
// Traffic light tester module.
//
// We clock the device as usual, supply reset, and eventually "push
// the walk button" to activate the traffic light.
//
// ============================================================

// `timescale 1 ns / 1 ns

module TestBench;

   reg  clk;     // Clock into the FPGA
   reg  walk;    // A button that causes the walk light to go on
   reg  reset;   // The reset line to your design

   wire green;   // The green light on Dodge Street
   wire yellow;  // The yellow light on ...
   wire red;     // The red light on ...
   wire go;      // The walk light for the pedestrian
   wire stop;    // The "don't walk" light

   // Here is your FPGA chip
   Traffic yourChip( reset, clk, walk, green, yellow, red, go, stop );
   // Provide clocking to the FPGA
   always
      begin
      #10 clk = ~clk;
      end


   // Start up code.
   initial
     begin
    clk = 0;
    walk = 0;
    reset = 1;
    #100 reset = 0;
     end

   // Eventually we want to "push the walk button" which causes the
   // traffic lights to cycle yellow, red, then back to green.
   // Also, we want to stop the sim at some point too. 
   initial
     begin
    #1000 walk = 1;
    #100  walk = 0;
    #100000 $stop;
     end

endmodule // QuasiTestBench
// =====================