七人表决器VHDL语言

七人表决器：七人表决，如果大于等于四人同意，则输出为1，否则输出为0。

LIBRARY IEEE; --七人表决器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY VOTE IS PORT(a,b,c,d,e,f,g:IN STD_LOGIC; o:OUT STD_LOGIC); END ENTITY VOTE; ARCHITECTURE VT OF VOTE IS BEGIN PROCESS(a,b,c,d,e,f,g) VARIABLE sum:INTEGER RANGE 0 TO 8; BEGIN IF a='1' THEN sum:=1; ELSE sum:=0; END IF; IF b='1' THEN sum:=sum+1; ELSE sum:=sum; END IF; IF c='1' THEN sum:=sum+1; ELSE sum:=sum; END IF; IF d='1' THEN sum:=sum+1; ELSE sum:=sum; END IF; IF e='1' THEN sum:=sum+1; ELSE sum:=sum; END IF; IF f='1' THEN sum:=sum+1; ELSE sum:=sum; END IF; IF g='1' THEN sum:=sum+1; ELSE sum:=sum; END IF; IF sum>=4 THEN o<='1'; ELSE o<='0'; END IF; END PROCESS; END ARCHITECTURE VT; LIBRARY IEEE;