My code consists of two files. One file has all the modules and one file has the test bench. When I try to run a simulation on the test bench, I get an unresolved reference error on this line in one of my modules:My code consists of two files. One file has all
阅读背景：
Verilog代码编译，但是为什么不运行模拟呢?
来源：互联网
分享到：
