工程中信号声明了
type defineVD_TYPE is array(50 downto 0) of std_logic_vector(7 downto 0); type defineVD_TYPE is array(50 down
type defineVD_TYPE is array(50 downto 0) of std_logic_vector(7 downto 0); type defineVD_TYPE is array(50 down
阅读背景：
VHDL中 定义信号数组 VD(50 DOWNTO 0),可以使用VD(i)<=VD(j)么
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