FPGA让数码管亮起来

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_1164.all;
entity led is
	port(
	clk:in std_logic;
		seg:out std_logic_vector(2 downto 0);
		duan:out std_logic_vector(7 downto 0)
	);
end entity;
architecture behavor of led is
type ram1 is array(0 to 9) of std_logic_vector(7 downto 0);
constant data:ram1 :=("01000000","01111001","00100100","00110000","00011001","00010010","00000010","01111000","00000000","00010000");--共阳极数码管对应0-9数字段值
signal n1,n2,n3,n4,n5:integer range 0 to 1000;
begin
seg<=CONV_STD_LOGIC_VECTOR( n5,3); --运用一个转换函数将整数转换为一个3位的位矢量
	process(clk)--duan kongzhi jincheng
	begin
	if clk'event and clk='1' then
		if n1<1000 then
			n1<=n1+1;
			else if n2<1000 then
				 n2<=n2+1;
				 n1<=0;
				 else if n3<30 then--开发板的频率是50Mhz,现在经过3000000分频，使数码管显示的间隔为0.6s
						n3<=n3+1;
						n2<=0;
						else
				  duan<=data(n4);--xianshi shuju
				  n3<=0;
				  if(n5<7) then
				      n5<=n5+1;;--改变数码管的位选
				      else
				      n5<=0;
				  end if;
				   
				  if n4<9 then
				      n4<=n4+1				library ieee;
use ieee.std_logic_1164.all;
use